Techmezine speaks with Tao Lang, Communication Business Unit – Senior Product Marketing Manager, Microchip Technology on Microchip’s META-DX2+ family.
- With the upgrade from 400G to 800G, what are the main development trends of global network infrastructure? What will be the main development characteristics of the physical layer of Ethernet? Also, what do you think are the challenges in interconnecting old and new co-existing devices?
Upgrading from 400G to 800G doubles the capacity of each port, but QSFP port size and the 8 electrical lanes remain the same. The key point is the evolution from 56 PAM4 to 112G PAM4 signaling. New switching and routing chips will interconnect at SerDes lanes up to 112G PAM4 and META-DX2+ enables those connections. Existing 400G optics in QSFP-DD form factor, such as 400GE or 400ZR optical modules, are now more affordable so META-DX2+ with the industry’s largest 1.6T gearbox capacity enables connecting of existing 400G optics (56G PAM4 per lane) with new devices operating at up to 112G PAM4 per lane.
2. What role will the new META-DX2+ family play in industry applications?
META-DX2+ plays key roles within applications such as cloud data center interconnect, enterprise switching and routing, and optical transport.
- Cloud data center interconnect benefits from META-DX2+ high capacity 1.6T total bandwidth, which is double the capacity of competitors when operating in gearbox mode, and encryption, which secures all data links while offloading centralized processors from that task.
- Enterprise switching and routing can leverage META-DX2+ to aggregate multiple low-rate ports, which allows the centralize processor or switch to run with higher throughout efficiency, while still providing encryption, PTP, and other features on all ports. IPsec encryption is increasingly valuable for enterprise customers as links across the network need end-to-end encryption at line rate.
- Optical transport systems use META-DX2+ to flexibly connect coherent optics, grey optics, and DAC cables with the internal crosspoint providing programmable options for connectivity over a wide range of Ethernet, OTN, and proprietary data rates.
3. Diverse needs are rising, including cloud data centers, AI/ML computing clusters, 5G and telecom service providers, as well as enterprise infrastructures. What are the different requirements for Ethernet PHY products from these different user types? Does the latest product family meet these requirements?
The META-DX2+ family addresses the needs of a broad range of equipment types, including cloud interconnect routers, enterprise ethernet switches, security appliances, AI/ML compute nodes, and optical transport systems. A common hardware and software design using META-DX2+ can be used across a wide range of products. Specific META-DX2+ features that address the needs of next-generation equipment include:
- 1.6T gearbox capacity – providing the smallest footprint PHY solution for 4x 400G ports, greater than 20% board savings compared to competing solutions that require two devices
- Integrated line-rate encryption using MACsec and IPsec to ensure that cloud data center and enterprise systems have end-to-end security
- XpandIO enables port aggregation of low-rate Ethernet clients over higher speed Ethernet interfaces, optimized for enterprise platforms
- IEEE 1588 Class C/D Precision Time Protocol (PTP) supports accurate nanosecond timestamping required for 5G backhaul and enterprise business critical services
- Proprietary data rate support and integrated crosspoint provides flexible connectivity between AI/ML processors
- ShiftIO crosspoint and OTN rate support enable the flexible connectivity needed in optical transport systems
4. Please share Microchip’s strengths and technical advantages in the Ethernet field, which has been incorporated in the new product family. Why do you focus on meeting customer’s needs by upgrading and improving the Ethernet physical layer portfolio?
META-DX2+ is our second generation of Ethernet PHY addressing Ethernet rates from 1G to 800G, building on the success of our META-DX1 device that supports rates from 1G to 400G. By adding 800G Ethernet rates, 112G PAM4 Serdes support, and encryption technology including MACsec and IPsec, our strength is that we provide devices with rich feature sets that can be used in multiple types of systems, so customers achieve real time-to-market savings by reusing META-DX2+ based hardware and software designs to across multiple product lines.
5. There is a general consensus in the industry that next-generation switches will require 112G SerDes or even 224G SerDes, what are your thoughts on this trend? What challenges will this bring for Ethernet physical layer system designs?
112G PAM4 SerDes are being used in many next-generation switches and optics because it enables a 2x benefit in port density over the previous generation, and it drives the need for a retimer/PHY to ensure good signal integrity. 224G SerDes is a logical step forward for the future, but it appears to be many years away, because the industry is still early in the transition to 112G.
6. Following the concerns on cost, power consumption and latency, etc., the industry is placing more and more emphasis on security. How does Microchip enhance product security while ensuring ease of use through collaborative design of hardware and software (hardware-software synergy)?
META-DX2+ supports line-rate encryption using MACsec and IPsec. As port rates continue to increase, encryption creates a significant load on a processor. META-DX2+ enables the offload of encryption from packet processors so that systems can more easily scale up to higher bandwidths with end-to-end security. The META-DX2+ family enables designs to reuse a common hardware footprint when building both encrypted and non-encrypted versions of the same design, all using the same SDK.
To ensure product security, the system boot image and the META-DX2+ firmware are verified using a ‘Root of Trust’ device such as the Microchip CEC1736, which is part of our total system solution recommendations on our website. ( www.microchip.com/META-DX2 )
